Planar or horizontal transistors are often used to fabricate integrated circuits (ICs). A planar transistor has a diffused source electrode and a drain electrode separated by a channel region. Overlying the channel region is a gate electrode that is separated from the channel region by a gate dielectric, which is typically a gate oxide. Planar transistors, although used and useful in many IC applications, are substrate area intensive and consume a large amount of substrate per transistor. In addition, with IC geometries decreasing into sub-micron ranges, planar transistors have various disadvantages. At smaller geometries and thinner gate oxide thicknesses, well documented problems such as hot carrier injection, leakage currents, isolation, short channel behavior, and channel length variations are major problems in planar transistors.
To overcome some of the disadvantages described above for planar transistors, elevated source and drain transistors, lightly doped drain (LDD) transistors, and other improvements were developed. Although the improvements reduced some of the disadvantages listed above, the improvements had some undesirable characteristics. The primary undesirable characteristic is the fact that the improved transistors were, in most cases, as area intensive or more area intensive than the planar transistor.
Various approaches have been used to try to reduce transistor surface area and increase transistor racking density by utilizing vertically oriented devices, while at the same time reducing some of the adverse effects described above. The surrounding gate transistor (SGT) was developed wherein a spacer gate and planar diffusions are used to form a transistor. The SGT reduced some of the disadvantages that affect planar transistors, and reduced surface area due to a vertically positioned spacer gate. Topography problems and the geometry of the SGT usually result in source and drain contacts that are difficult to achieve and are difficult to consistently produce using submicron technology. In addition, doping of source regions, drain regions, and channel regions via implants can be difficult due to geometry and may require special processing.
In order to further increase circuit density, the thin film transistor (TFT) has been developed, especially for memory applications. TFTs have been designed in both horizontal and vertical orientations to meet the needs of a particular application or layout constraint of, for instance, a memory cell. Although small memory cell areas can result from the use of TFTs, TFTs are highly resistive and therefore not adequate for all applications.
Despite the efforts that have been made in the area of three-dimensional integration of circuits, there continues to be a need for improvements. Examples of desired improvements include shorter interconnection distances between individual devices within the IC and reduced contact resistance of contacts made between individual devices or interconnections.